1. Field of the Invention
The present invention relates to a large scale semiconductor integrated circuit device, particularly to a large scale semiconductor integrated circuit device configuration with a high integration density, high speed of operation and low power consumption.
2. Description of the Prior Art
A continued advancement of electronic circuitry and electronic computer systems demands increased integration density and speed of operation of semiconductor integrated circuit devices.
As a means of realizing high integration density and high speed of operation a method for designing integrated circuits known as the master-slice technique is typically employed. The master-slice technique is described, for example, in the Feb. 20, 1976 issue of "Electronics," pages 136 to 139. Namely, individual unit circuit areas are located along the row and column directions at the surface of a semiconductor substrate, wiring channels (wiring tracks) are laid out between these unit circuit areas, the wiring between these unit circuit areas is generally formed within these wiring channels. According to this master-slice technique, an increase in the number of circuits provided within the unit circuit areas, and in the number of unit circuit areas formed in the semiconductor substrate, results in a semiconductor integrated circuit having higher integration density.
For example, U.S. Pat. No. 3,643,232 (issued Feb. 15, 1972) discloses that functional elements or cells (corresponding to the unit circuit areas) are defined with proper separation in the form of an array in the row and column directions on the surface of a semiconductor substrate, the wiring of each functional element or each cell being made by a first wiring layer and the wiring between the different cells being made by a second wiring layer. By such means, the operable cells formed with the first wiring layer may be interconnected by the second wiring layer, and a logic circuit having the desired logic function can thus be formed in the semiconductor substrate. According to such a prior art technique, a large scale integrated circuit having only operable circuits can be formed within a semiconductor substrate.
The basic approach of such a general master-slice technique is well known, but the configuration and means for realizing the currently demanded higher integration density and high speed of operation is not suggested by the prior art.
For example, the U.S. Pat. No. 3,808,475 (issued Apr. 30, 1974) discloses a large scale semiconductor integrated circuit device comprising 100 emitter coupled logic (ECL) circuits within a single semiconductor substrate which allows a signal transfer delay time of 2 ns or less. The large scale semiconductor integrated circuit device disclosed in this U.S. Patent involves basic logic circuits with emitter coupled logic (ECL). This circuit device has 25 macros (each corresponding to said unit circuit area, functional element or cell), where a total of four ECLs are included in each unit circuit area, the macros being arrayed with adequate separation gap in row and column directions on a single semiconductor substrate surface. The wiring between the macros, for connecting the power supply (V.sub.EE) and for connecting the components within each macro, comprises a first wiring layer extending in the row direction while connection of the macros and the wiring for grounding (V.sub.CC) is provided by the second wiring layer extending in the column direction. Larger transistors are arranged between the macros and the output terminal pads, for outputing the emitter-follower circuits. Moreover, the width of the ground (V.sub.CC) wiring and the power supply (V.sub.EE) wiring is adjusted to provide resistance ratios of between 3 to 1 and 4 to 1, to compensate (or track) for voltage change due to a macro's position and the temperature distribution in the semiconductor substrate.
With such a configuration for a large scale semiconductor integrated circuit device, some improvement has been realized in integration density and operating speed, the improvement being in many cases sufficient to provide the performance required of currently known electronic devices. But with this approach it will be difficult to satisfy the performance to be required for practical use in the future. Particularly, since macros are arrayed on a single semiconductor substrate with some interval in both row and column directions, any improvement in integration density is limited.
In addition, within the large scale semiconductor integrated circuit elements, one may provide macros comprising logic circuits terminating within the semiconductor integrated circuit device itself, and macros for forming logic circuits to be connected to external circuits outside of the semiconductor integrated circuit device. All the macros may be formed by using an impurity diffusion mask with a repeated pattern, as a result of which the size of the transistors and resistors of each macro, and the impurity concentration etc., are the same for all macros. Therefore, even for the macros for internal termination, which could be driven with lower electrical power, a considerable amount of power is consumed, an amount equal to that consumed by the macros for external circuit output, which are driven with large amounts of electrical power. All the macros in such a semiconductor integrated circuit device consume large amounts of electrical power, thus necessitating a large capacity power supply and a large size heat sink.